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UCB1400
Audio codec with touch screen controller and power management monitor
Rev. 02 -- 21 June 2002 Product data
1. General description
The UCB1400 is a stereo audio codec equipped with touch screen and power management interfaces. It integrates an AC '97 Rev. 2.1 interface for communication to an AC link host controller such as the Intel XscaleTM processor. The stereo audio codec inputs connect directly to a microphone or line level sources such as a CD player. The stereo audio codec outputs at line level and can drive a headphone directly. The touch screen interface connects directly to a 4-wire resistive touch screen. A built-in 10-bit analog-to-digital converter provides readout of touch screen and power management parameters. Ten general-purpose I/O pins provide programmable inputs and/or outputs to the system.
2. Features
s 48-pin LQFP surface mount package and low external component count for minimal PCB space requirement s Integrated AC '97 Rev. 2.1 interface s 20-bit stereo audio codec supporting programmable sample rates, and input/output gain control x Stereo line input and mono microphone input x Stereo line/headphone output with bass/treble control x Headphone driver with short circuit protection and virtual ground for DC coupling s 4-wire resistive touch screen interface circuit supporting position, pressure and plate resistance measurements s 10-bit successive approximation ADC with internal track-and-hold circuit and analog multiplexer for touch screen readout and monitoring of four external high voltage (7.5 V) sources s Ten general purpose input/output pins s 3.3 V supply voltage and built-in power saving modes for portable and battery powered applications.
3. Applications
s s s s s Smart mobile phones Handheld PCs Palm-top PCs Personal Intelligent Communicators (PIC) Personal Digital Assistants (PDA).
Philips Semiconductors
UCB1400
Audio codec with touch screen controller and power management monitor
4. Ordering information
Table 1: Ordering information Package Name UCB1400BE LQFP48 Description Plastic low profile quad flat package, 48 leads; body 7 x 7 x 1.4 mm Version SOT313-2 Type number
5. Block diagram
AD[3:0]
TSPX TSMX TSPY TSMY TOUCH I/F MUX
VOLTAGE REFERENCE
10-BIT ADC
SDATA_IN SDATA_OUT ADCSYNC AC LINK I/O AND CONTROL BIT_CLK RESET SYNC IRQOUT
XTL_IN OSC XTL_OUT 2-CHANNEL 20-BIT AUDIO DAC LINE_OUT_L, LINE_OUT_R
IO[9:0]
DIGITAL I/O
2-CHANNEL 20-BIT AUDIO ADC
LINE_IN_L, LINE_IN_R, MICP MICGND
SN00236
Fig 1. Block diagram.
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Product data
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UCB1400
Audio codec with touch screen controller and power management monitor
6. Pinning information
6.1 Pinning
38 AVDD3
42 AVSS3
48 IO9
47 IO8
46 IO7
45 IO6
44 IO5
43 IO4
41 IO3
40 IO2
39 IO1
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2
1 2 3 4 5 6
37 IO0 36 35 34 33 32 31
LINE_OUT_R LINE_OUT_L VREFDRV AVSS2 AVDD2 VADCN VREFBYP IRQOUT VADCP VREF AVSS1 AVDD1
UCB1400
7 8 9 30 29 28 27 26 25 AD3 13 AD2 14 AD1 15 AD0 16 TSPX 17 TSMX 18 TSMY 19 TSPY 20 MICP 21 MICGND 22 LINE_IN_L 23 LINE_IN_R 24
SYNC 10 RESET 11
ADCSYNC 12
SN00219
Fig 2. Pin configuration (LQFP48).
6.2 Pin description
Table 2: Pin description Total pin count = 48 Symbol Pin Type Default state - - - - 0 - 0 0 Description
AC-link, crystal and interrupt interface (pin count = 8) XTL_IN XTL_OUT RESET SYNC BIT_CLK SDATA_OUT SDATA_IN IRQOUT 2 3 11 10 6 5 8 29 I O I I O I O O 24.576 MHz crystal / master clock input 24.576 MHz crystal AC-link master reset AC-link sample sync AC-link 12.288 MHz serial data clock AC-link serial data output. UCB1400 input stream AC-link serial data input. UCB1400 output stream Interrupt output
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UCB1400
Audio codec with touch screen controller and power management monitor
Table 2: Pin description...continued Total pin count = 48 Symbol Pin Type Default state - closed - - driver off driver off - Hi-Z Hi-Z Hi-Z Hi-Z - Input Description
Audio interface (pin count = 6) MICP MICGND LINE_IN_L LINE_IN_R LINE_OUT_L LINE_OUT_R AD[3:0] TSPX TSMX TSMY TSPY ADCSYNC IO[9:0] 21 22 23 24 35 36 13, 14, 15, 16 17 18 19 20 12 48, 47, 46, 45, 44, 43, 41, 40, 39, 37 9, 1 I I I I O O I I/O I/O I/O I/O I I/O Microphone input Microphone ground switch input Line in left channel Line in right channel Line out left channel Line out right channel Analog voltage input Touch screen positive X-plate Touch screen negative X-plate Touch screen negative Y-plate Touch screen positive Y-plate ADC synchronization pulse General purpose input/output
ADC and touch screen interface (pin count = 9)
GPIO interface (pin count = 10)
Power and miscellaneous (pin count = 15) DVDD2, DVDD1 AVDD3, AVDD2, AVDD1 S S S - - - Digital supply Digital ground Analog supply
DVSS2, DVSS1 7, 4 38, 32, 25
AVSS3, 42, AVSS2, AVSS1 33, 26 VREFDRV VREF VADCP VADCN VREFBYP 34 27 28 31 30
S O O S S I/O
- - - - - Hi-Z
Analog ground Reference voltage for headphone drivers Reference voltage Audio ADC positive reference voltage Audio ADC negative reference voltage Reference bypass output/ external reference voltage input
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Product data
Rev. 02 -- 21 June 2002
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UCB1400
Audio codec with touch screen controller and power management monitor
7. Functional description
7.1 Functional block diagram
LINE_OUT_L
MASTER VOL. 0-94.5 dB (0x02)
DAC_L VARIABLE RATE (0x2A, 0x2C) INTERPOLATION FILTER & NOISE SHAPER DSP (0x6A)
LINE_OUT_R
MASTER VOL. 0-94.5 dB (0x02)
DAC_R VARIABLE RATE (0x2A, 0x2C) LOOP BACK (0x20)
LINE_IN_L MUX (0x1A) MICP 0-22.5 dB (0x0E) RECORD GAIN 0-22.5 dB (0x1C) ADC_L VARIABLE RATE (0x2A, 0x32)
DECIMATION FILTER RECORD GAIN 0-22.5 dB (0x1C) ADC_R VARIABLE RATE (0x2A, 0x32)
LINE_IN_R
OVFL RESET SYNC DIGITAL INTERFACE
MICGND
GROUND SWITCH (0x1A) ADC / TOUCH POWER UP/DOWN (0x64, 0x66) OSCILLATOR / PLL AC97 / AUDIO POWER UP/DOWN (0x26, 0x6C)
BIT_CLK SDATA_OUT SDATA_IN
XTL_IN XTL_OUT
IRQOUT
IO[9:0]
IO BLOCK DATA (0x5A) DIRECTION (0x5C) TOUCH SCREEN BIASING MATRIX (0x64)
IO DATA
INTERRUPT GENERATION POSITIVE (0x5E) NEGATIVE (0x60) STATUS/CLEAR (0x62) BIAS CURRENT ADC READY
INTERRUPT
TSPX TSMX TSPY TSMY AD[3:0] ADCSYNC
MUX (0x64, 0x66)
ADC CONTROL (0x66) DATA (0x68)
ADC DATA
SN00243
Fig 3. Functional block diagram.
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Product data
Rev. 02 -- 21 June 2002
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UCB1400
Audio codec with touch screen controller and power management monitor
8. AC '97 interface
The UCB1400 implements an AC '97 Revision 2.1 interface. Refer to the Audio Codec '97 Component Specification Revision 2.1 from Intel.
SYNC BIT_CLK SDATA_OUT AC97 CONTROLLER SDATA_IN RESET IRQOUT
UCB1400
SN00237
Fig 4. UCB1400 and AC '97 controller connection diagram.
8.1 Clocking
The UCB1400 functions only as a primary codec. As such, it derives its clock internally from an externally attached 24.576 MHz crystal or clock oscillator, and drives a buffered and divided down (12) clock to its digital companion controller over AC-link under the signal name "BIT_CLK". The beginning of all audio sample packets, or Audio Frames, transferred over AC-link is synchronized to the rising edge of the SYNC signal. SYNC is driven by the AC '97 Controller. The AC '97 Controller takes BIT_CLK as an input and generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This yields a 48 kHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-link on every rising edge of BIT_CLK, and subsequently sampled on the receiving side of AC-link on each immediately following falling edge of BIT_CLK.
8.2 Resetting UCB1400
The UCB1400 recognizes the following types of reset:
* Cold reset: where all UCB1400 logic (registers included) is initialized to its default
state. Initiated by bringing RESET LOW for at least 1 s.
* Warm reset: where the contents of the UCB1400 register set are left unaltered.
Initiated by bringing SYNC HIGH for at least 1 s without BIT_CLK. Initiated by a write to register 0x00. After signaling a reset to UCB1400, the AC '97 Controller should not attempt to play or capture audio data until it has sampled a "Codec Ready" indication from UCB1400.
* Register reset: which only initializes the UCB1400 registers to their default states.
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Product data
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UCB1400
Audio codec with touch screen controller and power management monitor
8.3 Digital interface
8.3.1 AC-link digital serial interface protocol The UCB1400 incorporates a 5-pin digital serial interface that links it to the AC '97 Controller. AC-link is a bi-directional, fixed rate, serial PCM digital stream. It handles multiple input, and output audio and modem streams, as well as control register accesses employing a time division multiplexed (TDM) scheme. The AC-link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. The control and data slots defined by UCB1400 include:
* * * * * * *
SDATA_OUT TAG (output slot 0) SDATA_IN TAG (input slot 0) Control (CMD ADDR & DATA) write port (output slots 1, 2) Status (STATUS ADDR & DATA) read port (input slots 1, 2) PCM L & R DAC playback (output slots 3, 4) PCM L & R ADC record (input slots 3, 4) GPIO interrupt status (input slot 12)
The AC-link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream, and contains valid data. SYNC remains HIGH for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The portion of the audio frame where SYNC is HIGH is defined as the Tag Phase. The remainder of the audio frame where SYNC is LOW is defined as the "Data Phase". Additionally, for power savings, all clock, sync, and data signals can be halted. UCB1400 is implemented as a static design to allow its register contents to remain intact when entering a power savings mode.
SLOT # SYNC
0
1
2
3
4
5
6
7
8
9
10
11
12
SDATA_OUT
TAG CODEC ID
CMD ADDR
CMD DATA
PCM L
PCM R
LINE 1 DAC
PCM CENTER
PCM L SURR
PCM R SURR
PCM LFE
LINE 2 DAC PCM L (n+1)
HSET DAC PCM R (n+1)
IO CTRL PCM C (n+1)
SDATA_IN
TAG
STATUS ADDR
STATUS DATA
PCM L
PCM R
LINE 1 ADC
MIC ADC
RSRVD
RSRVD
RSRVD
LINE 2 ADC
HSET ADC
IO STATUS
SLOTREQ 3-12
SN00220
Fig 5. Standard bi-directional audio frame.
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UCB1400
Audio codec with touch screen controller and power management monitor
8.3.2
AC-link audio output frame (SDATA_OUT) The audio output frame data streams correspond to the multiplexed bundles of all digital output data targeting UCB1400's DAC inputs, and control registers. Each audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16 bits which are used for AC-link protocol infrastructure. Slot 0: TAG: Within slot 0, the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the entire audio frame. If the `Valid Frame' bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. The next 12 bit positions sampled by UCB1400 indicate which of the corresponding 12 time slots contain valid data. In this way, data streams of differing sample rates can be transmitted across AC-link at its fixed 48 kHz audio frame rate. Figure 6 illustrates the time slot based AC-link protocol. (Note that Bits 1 and 0 of slot 0 tag phase are used for primary/secondary codec addressing as described in Section 8.4.
20.8 s (48 kHz) TAG PHASE SYNC BIT_CLK SDATA_OUT END OF PREVIOUS AUDIO FRAME VALID FRAME
slot(1) slot(2) slot(12) "0" * * 19 0 19 0 19 0 19 0
DATA PHASE
81.4 ns (12.288 MHz)
TIME SLOT "VALID" BITS ("1" = TIME SLOT CONTAINS VALID PCM DATA)
SLOT 1
SLOT 2
SLOT 3
SLOT 12
SN00221
* See Table 4.
Fig 6. AC Link audio output frame.
A new audio output frame begins with a LOW-to-HIGH transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the UCB1400 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC '97 Controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by UCB1400 on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
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UCB1400
Audio codec with touch screen controller and power management monitor
AC '97 SAMPLES SYNC ASSERTION HERE SYNC
AC '97 SAMPLES FIRST SDATA_OUT BIT OF FRAME HERE
BIT_CLK
SDATA_OUT
END OF PREVIOUS AUDIO FRAME
VALID FRAME
slot(1)
slot(2)
SN00222
Fig 7. Start of an audio output frame.
SDAT_OUT's composite stream is MSB justified (MSB first) with all non-valid slots' bit positions stuffed with 0s by the AC '97 Controller. If there are less than 20 valid bits within an assigned and valid time slot, the AC '97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s. Slot 1: Command address port: The command port is used to control features, and monitor status (see Section 8.3.3 "AC-link audio input frame (SDATA_IN)", Slots 1 and 2) for AC '97 functions including, but not limited to, sample rate, codec configuration, and power management. The control interface architecture supports up to 64 16-bit read/write registers, addressable on even byte boundaries, and reserves support for 64 odd addresses, as described in AC '97 2.1 Component Specification Appendix D. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h, 03h, etc.) accesses are reserved. Note that shadowing of the control register file on the AC '97 Controller is an option left open to the implementation of the AC '97 Controller. UCB1400's control register file is readable as well as writable to provide more robust testability. Audio output frame slot 1 communicates control register address, and write/read command information to the UCB1400. Command Address Port bit assignments are:
* Bit(19) Read/write command (1 = read, 0 = write). * Bit(18:12) Control register index (64 16-bit locations, addressed on even byte
boundaries)
* Bit(11:0) Reserved (stuffed with 0s)
The first bit (MSB) sampled by UCB1400 indicates whether the current control transaction is a read or a write operation. The following 7 bit positions communicate with the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC '97 Controller.
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Audio codec with touch screen controller and power management monitor
Slot 2: Command data port: The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by Slot 1, bit 19).
* Bit(19:4) Control Register Write Data (stuffed with 0s if current operation is a read). * Bit(3:0) Reserved (stuffed with 0s)
If the current command port operation is a read, then the entire slot time must be stuffed with 0s by the AC '97 Controller. Slot 3: PCM playback left channel: Audio output frame slot 3 is the composite digital audio left playback stream. Typically, this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC '97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20 bits is transferred, the AC '97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s. Slot 4: PCM playback right channel: Audio output frame slot 4 is the composite digital audio right playback stream. Typically, this slot is composed of standard PCM (.wav) output samples digitally mixed (on the AC '97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20 bits is transferred, the AC '97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s. Slots 5 through 12: All other audio output frame slots are ignored by the UCB1400. 8.3.3 AC-link audio input frame (SDATA_IN) The audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AC '97 Controller. As is the case for audio output frame, each AC-link audio input frame consists of 12, 20-bit time slots. Slot 0 is a special reserved time slot containing 16 bits, which are used for AC-link protocol infrastructure. Slot 0: TAG: Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether UCB1400 is in the `Codec Ready' state or not. If the `Codec Ready' bit is a 0, this indicates that UCB1400 is not ready for normal operation. This condition is normal following the deassertion of power-on reset, for example, while UCB1400's voltage references settle. When the AC-link `Codec Ready' indicator bit is a logic 1, it indicates that the AC-link and UCB1400 control and status registers are in a fully operational state. The AC '97 Controller must further probe the Power-down Control/Status Register (0x26) to determine exactly which subsections, if any, are ready. Prior to any attempts at putting UCB1400 into operation, the AC '97 Controller should poll the first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that the UCB1400 has gone `Codec Ready'. Once the UCB1400 is sampled `Codec Ready' then the next 12 bit positions sampled by the AC '97 Controller indicate which of the corresponding 12 time slots are assigned to input data streams, and that they contain valid data. Figure 8 illustrates the time slot based AC-link protocol.
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Audio codec with touch screen controller and power management monitor
20.8 s (48 kHz) TAG PHASE SYNC BIT_CLK SDATA_IN END OF PREVIOUS AUDIO FRAME CODEC READY
slot(1) slot(2) slot(12) "0" "0" "0" 19 0 19 0 19 0 19 0
DATA PHASE
81.4 ns (12.288 MHz)
TIME SLOT "VALID" BITS ("1" = TIME SLOT CONTAINS VALID PCM DATA)
SLOT 1
SLOT 2
SLOT 3
SLOT 12
SN00223
Fig 8. AC-link audio input frame.
A new audio input frame begins with a LOW-to-HIGH transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, UCB1400 samples the assertion of SYNC. This falling edge marks the time when both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of BIT_CLK, UCB1400 transitions SDATA_IN into the first bit position of slot 0 (`Codec Ready' bit). Each new bit position is presented to AC-link on a rising edge of BIT_CLK, and subsequently sampled by the AC '97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.
AC '97 SAMPLES SYNC ASSERTION HERE SYNC
AC '97 CONTROLLER SAMPLES FIRST SDATA_IN BIT OF FRAME HERE
BIT_CLK
SDATA_IN
END OF PREVIOUS AUDIO FRAME
CODEC READY
slot(1)
slot(2)
SN00224
Fig 9. Start of an audio input frame.
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for assigned and/or unassigned time slots) stuffed with 0s by the UCB1400. SDATA_IN data is sampled on the falling edges of BIT_CLK.
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Slot 1: Status address port: The status port is used to monitor status for UCB1400 functions including, but not limited to, codec settings and power management. Audio input frame slot 1's stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1 and 2 had been tagged `valid' by UCB1400 during slot 0.) Status address port bit assignments are:
* Bit(19) Reserved (stuffed with 0s) * Bit(18:12) Control register index (echo of register index for which data is being
returned)
* Bit(11:2) SLOTREQ bits: Only bits 11 and 10 (PCM L & R) shall be used by
UCB1400. All unused bits shall be stuffed with 0s.
* Bit(1, 0) Reserved (stuffed with 0s)
The first bit (MSB) generated by UCB1400 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, the next 10 bits are the SLOTREQ bits, two of which (bits 11 and 10) are used by UCB1400 to request data using the variable sample rate signaling protocol as defined in the AC '97 Component Specification. The trailing 2 bit positions are stuffed with 0s by UCB1400. Slot 2: Status data port: The status data port delivers 16-bit control register read data.
* Bit(19:4) Control register read data (stuffed with 0s if tagged `invalid' by UCB1400) * Bit(3:0) Reserved (stuffed with 0s)
If slot 2 is tagged invalid by UCB1400, then the entire slot will be stuffed with 0s by UCB1400. Slot 3: PCM record left channel: Audio input frame slot 3 is the left channel output of UCB1400's input MUX, post-ADC. The UCB1400's ADCs are implemented to support 20-bit resolution. UCB1400 ships out its ADC output data (MSB first) to fill out its 20-bit time slot. Slot 4: PCM record right channel: Audio input frame slot 4 is the right channel output of UCB1400's input MUX, post-ADC. The UCB1400's ADCs are implemented to support 20-bit resolution. UCB1400 ships out its ADC output data (MSB first) to fill out its 20-bit time slot. Slot 12: GPIO status: Audio output frame slot 12 is used to carry modem GPIO input data. Table 3 shows the definition by AC '97 Component Specification. The UCB1400 does not make use of slot 12 to report its IO pin status. It only uses the GPIO_INT as an optional means (when the GIEN bit is set in the Feature CSR1 register) to signify an interrupt event (in addition to pin IRQOUT).
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Slot 12 definition GPIO GPIO[15:0] Vendor rsrvd GPIO_INT in Name Sense in/out Description Modem GPIO as defined by the Intel AC '97 Component Specification. Vendor optional. GPIO_INT (uses same logic as wake-up event)
Table 3: Bit 19-4 3-1 0
Slots 5 through 11: All other audio input frame slots shall be stuffed with 0s by the UCB1400. 8.3.4 AC-link low power mode The AC-link signals can be placed in a low power mode. When the UCB1400's PR4 bit is set to `1' in the Power-down status and control register (0x26), both BIT_CLK and SDATA_IN will be brought to, and held at, a logic LOW voltage level.
SYNC
BIT_CLK
SDATA_OUT
slot 12 prev. frame
TAG
Write to 0x26
Data PR4
SDATA_IN
slot 12 prev. frame
TAG
SN00244
Fig 10. AC-link power-down timing.
BIT_CLK and SDATA_IN are transitioned low immediately following the decode of the write to Register 0x26 with PR4. When the AC '97 Controller driver is at the point where it is ready to program the AC-link into its low power mode, slots (1 and 2) are assumed to be the only valid stream in the audio output frame. The AC '97 Controller should also drive SYNC and SDATA_OUT LOW after programming UCB1400 AC '97 to this low power, halted mode. The AC '97 Controller is required to drive and keep SYNC and SDATA_OUT LOW in this low power, halted mode. Once the UCB1400 has been instructed to halt BIT_CLK, a special `wake-up' protocol must be used to bring the AC-link to the active mode since normal audio output and input frames cannot be communicated in the absence of BIT_CLK.
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Waking up the AC-link: There are two methods for bringing the AC-link out of a low power, halted mode. Regardless of the method, it is the AC '97 Controller that performs the wake-up task. AC-link protocol provides for a `Cold AC '97 Reset', and a `Warm AC '97 Reset'. The current power-down state would ultimately dictate which form of AC '97 reset is appropriate. Unless a `cold' or `register' reset (a write to the Reset register) is performed, wherein the UCB1400 registers are initialized to their default values, registers are required to keep state during all power-down modes. Once powered down, re-activation of the AC-link via re-assertion of the SYNC signal must not occur for a minimum of four audio frame times following the frame in which the power-down was triggered. When AC-link powers-up, it indicates readiness via the Codec Ready bit (input slot 0, bit 15). Cold AC '97 reset: A cold reset is achieved by asserting RESET for the minimum specified time. By driving RESET LOW, all UCB1400 control registers will be initialized to their default power-on reset values. BIT_CLK and SDATA_OUT will be activated, or re-activated as the case may be. RESET is an asynchronous input to the UCB1400. Warm AC '97 reset: A warm AC '97 reset will re-activate the AC-link without altering the current AC '97 register values. A warm reset is signaled, in the absence of BIT_CLK, by driving SYNC HIGH for a minimum of 1 s. Within normal audio frames, SYNC is a synchronous input to the UCB1400. However, in the absence of BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the UCB1400. The UCB1400 must not respond with the activation of BIT_CLK until SYNC has been sampled LOW again by the UCB1400. This will preclude the false detection of a new audio frame.
8.4 Accessing the UCB1400
The UCB1400 supports only primary codec configuration. Typically, the UCB1400 expects a 24.576 MHz crystal across the XTL_IN and XTL_OUT pins. Alternatively, an external 24.576 MHz clock can be applied to XTL_IN.
Table 4: Bit 15 14 13 12-3 2 1-0 AC-link audio output frame slot 0 bit allocation Description Frame valid Slot 1 valid command address bit (primary codec only) Slot 2 valid command data bit (primary codec only) Slot 3-12 valid bits as defined by AC '97 Component Specification Reserved (set to 0) 2-bit codec ID field 00 reserved for primary 01, 10, 11 indicate secondary
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UCB1400
Audio codec with touch screen controller and power management monitor
In order for the AC '97 Digital Controller to access the UCB1400, the 2-bit Codec ID field (chip select) (LSBs of Output Slot 0) must be set to `0' (see Table 4). The UCB1400 shall monitor the Frame Valid, Slot 1 Valid Command Address, Slot 2 Valid Command Data and Codec ID bits, and respond only if properly accessed by the AC '97 Digital Controller, as illustrated in Table 5. Note that although SLOTREQ bits reside in slot 1, they have validity independent of the tag bit for Valid Slot 1 Address. The UCB1400 shall only set SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to `1' when returning valid data from a previous register read, regardless of the validity of SLOTREQ bits (see also Section 8.5).
Table 5: Function UCB1400 response to AC '97 digital controller access Slot 0, bit 15 (Valid frame) 1 Slot 0, bit 14 (Valid Slot 1 address) 1 Slot 0, bit 13 (Valid Slot 2 data) 0 Slot 0, bits 1-0 (codec ID) 00 Action
AC '97 digital controller primary read frame N, SDATA_OUT UCB1400 status frame N+1, in response to AC '97 digital controller primary read frame N, SDATA_IN AC '97 digital controller primary write frame N, SDATA_OUT UCB1400 status frame N+1, in response to AC '97 digital controller primary write frame N, SDATA_IN
AC '97 controller reads UCB1400 register UCB1400 returns register status
1
1
1
00
1
1
1
00
AC '97 controller writes UCB1400 register UCB1400 writes register internally and returns nothing AC '97 controller reads or writes secondary codec UCB1400 ignores commands and returns nothing
1
0
0
00
AC '97 digital controller 1 secondary read or write frame N, SDATA_OUT UCB1400 status frame N+1, 1 in response to AC '97 digital controller secondary read or write frame N, SDATA_IN
0
0
01, 10 or 11
0
0
00
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8.5 Variable sample rate signaling protocol
The AC-link is defined for a fixed transfer rate of 48 kHz. To support the diverse sample rates, UCB1400 implements the Variable Sample Rate Signaling Protocol of the AC '97 Component Specification:
* To control the AC '97 Controller to input a rate other than 48 kHz, the UCB1400
uses the tag bit for slot 3 and 4 (PCM L & R) to indicate whether valid data is present or not.
* To control the AC '97 Controller to output a rate other than 48 kHz, the UCB1400
uses the active-low SLOTREQ bit for slot 3 and slot 4 (PCM L & R) to indicate whether it needs data from the AC '97 Controller. 8.5.1 SLOTREQ protocol To control the AC '97 Controller to output a rate other than 48 kHz, the UCB1400 examines its sample rate control registers, the state of its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to determine which SLOTREQ bits to set active (LOW). SLOTREQ bits asserted during the current audio input frame signal which active output slots require data from the AC '97 Digital Controller in the next audio output frame. An active output slot is defined as any slot supported by UCB1400 that is not in a power-down state. In case of UCB1400, the only SLOTREQ bits used are that for slot 3 and slot 4 request (bits 11 and 10 of input slot 1). SLOTREQ bits for all other slots shall be stuffed with 0s by UCB1400. Note that although SLOTREQ bits reside in slot 1, their validity does not depend on the tag bit for Valid Slot 1 Address (see also Section 8.4).
8.6 Wake-up support
Pressing the touch screen is an example of events that might need to wake-up the host CPU that has suspended into a low power state. Figure 11 shows the AC Link power-down/power-up sequence. The UCB1400 powers down the AC Link subsequent to its PR4 bit being programmed to 1. When enabled to wake on, e.g., a touch screen event, a wake event causes the UCB1400 to transition IRQOUT from LOW to HIGH. The system controller can use this information as a signal to wake up. Subsequently, the first thing that the device driver must do to reestablish communications with the UCB1400 is to command the AC '97 Digital Controller to execute a warm reset to the AC Link. Alternatively, if the GIEN bit in the Feature CSR1 register (0x6A) is set, a wake event will cause the UCB1400 to transition its SDATA_IN from LOW to HIGH. The UCB1400 shall keep SDATA_IN HIGH until it has sampled SYNC having gone HIGH, and then LOW.
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POWER-DOWN FRAME
SLEEP STATE
WAKE EVENT
NEW AUDIO FRAME
SYNC
BIT_CLK
SDATA_OUT
slot 12
prev. frame
TAG
Write to 0x26
Data PR4
TAG
Slot 1
Slot 2
SDATA_IN
slot 12
prev. frame
TAG
TAG
Slot 1
Slot 2
IRQOUT
SN00251
Fig 11. AC Link power-down/power-up sequence.
Before enabling wake-up via IRQOUT or GIEN bit, the UCB1400 must be enabled for interrupt by setting the appropriate bits in the Positive INT Enable register (0x5E) and Negative INT Enable register (0x60). The INT Clear/Status register (0x62) should then be cleared of any previous interrupts before going to low-power mode.
8.7 Test modes
AC '97 Component Specification defines two test modes. One is for ATE in-circuit test, and the other if for vendor-specific tests. The UCB1400 enters the ATE in-circuit test mode if SDATA_OUT is sampled HIGH at the trailing edge of RESET. The UCB1400 enters the vendor-specific test mode when coming out of reset if SYNC is HIGH. These cases will never occur during standard operating conditions. Regardless of the test mode, the AC '97 Controller must issue a cold reset to resume normal operation of the UCB1400.
8.7.1 ATE in-circuit test mode When the UCB1400 is placed in the ATE test mode, its digital AC-link outputs (i.e., BIT_CLK and SDATA_IN) shall be driven to a high impedance state. This allows ATE in-circuit testing of the AC '97 Controller. 8.7.2 Vendor-specific test mode When the UCB1400 is placed in the vendor-specific test mode, the Test Control register (Index 0x6E) determines the kind of tests to be performed. Refer to Section 12 "Register definition" for details.
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8.8 General purpose IOs
IOD[x]
IO DATA[x] (WRITE)
IO[x]
IO DATA[x] (READ)
TO INTERRUPT MODULE
SN00225
Fig 12. Block diagram of IO pin circuitry.
The UCB1400 has 10 programmable digital input/output (I/O) pins. These pins can be independently programmed as input or output using the IOD[9:0] bits in the IO Direction Register (0x5C). The output data is determined by the content of the IO[9:0] bits in the IO Data Register (0x5A), while the actual status of these pins can be read from the same register bits. The data on the IO[9:0] pins are fed into the interrupt control block, where they can generate an interrupt on the rising and/or falling edge of these signals.
8.9 Interrupt generation
The UCB1400 contains a programmable interrupt control block, which can generate an interrupt for a 0-to-1 and/or 1-to-0 transition on one or more of the IO[9:0] pins, the audio overload detection, the ADC Ready signal, and the TSPX and TSMX signals.
xxxP `1' D OR TREE R IRQOUT
INTERRUPT SOURCE xxx
D xxxN R xxxS READ GIEN
TO AC97 GPIO_INT AND WAKE-UP BLOCK
xxxS WRITE `1' RESET
SN00239
Fig 13. Block diagram of the interrupt controller.
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The interrupt generation mode is set by the Positive INT Enable Register (0x5E) and Negative INT Enable Register (0x60). The actual interrupt status of each signal can be read from the INT Clear/Status Register (0x62). The interrupt status is cleared whenever a `1' is written in the INT Clear/Status Register (0x62) for the corresponding bit. The interrupt controller is implemented asynchronously. This provides the possibility to generate interrupts when the BIT_CLK is stopped, e.g., an interrupt can be generated in power-down mode when the touch screen is pressed or when the state of one of the IO pins changes. The IRQOUT pin presents the `OR' function of all interrupt status bits and can be used to give an interrupt to the system controller. When the GIEN bit of the Feature Control/Status Register 1 (0x6A) is set, the IRQOUT signal is communicated to the AC Link by means of:
* GPIO_INT bit of input slot 12 when BIT_CLK is on. * Rising SDATA_IN when BIT_CLK is off.
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9. Audio codec
BB, TR, DE, ML, MR, MM
LINE_OUT_L HEADPHONE DRIVER
FSDAC NOISE SHAPER FSDAC INTERPOLATION FILTER DSP FEATURES 0 1 LPBK
LEFT, RIGHT FROM AC LINK
VREFDRV
LINE_OUT_R
DR, AR DAC CLOCKS 24.576 MHz PLL CLOCK MODULE ADC CLOCKS
GR LINE_IN_R PGA GL SR = LINE_IN_L LINE_IN_L PGA 1 0/20 dB MICP LNA ADC 0 ADC
SR = LINE_IN_R 1 0
DC, HIPS, GL, GR, RM
DECIMATION FILTER LEFT, RIGHT
TO AC LINK
OVFL OVERLOAD DETECTION
MICGND (SL = MIC) & NOT POWERED DOWN
SN00245
Fig 14. Audio codec block diagram.
9.1 ADC analog front-end
The analog front-end of the UCB1400 consists of one stereo ADC with a selector in front of it. Using this selector, one can either select the microphone input with a dedicated Low Noise Amplifier (LNA), or the line input with a Programmable Gain Amplifier (PGA). Via appropriate AC '97 register settings, the following modes can be supported:
* Standby mode: all PGAs, LNA and ADCs are powered down. * Stereo line in mode: the PGAs are used, and the LNA is powered down. * Microphone mode: the PGAs and right channel ADC are powered down, and
MICGND switch is on. The mono microphone signal can be sent to both left and right input of the decimation filter via a MUX in front of the decimation input.
* One line-in and one microphone mode: the left PGA is powered down.
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9.1.1
Line inputs The analog front-end of the UCB1400 consists of two stereo ADCs with a programmable gain stage. The full scale input voltage of the line input path is programmable in 1.5 dB steps independently for the left and right channels by setting the GL[3:0] and GR[3:0] bits in the Record Gain Register (0x1C).
9.1.2
Microphone input The UCB1400 audio codec input path accepts microphone signals via a DC blocking capacitor. The `ground' side of the microphone is either connected to the analog ground (AVSS) or to the MICGND pin of the UCB1400. The latter will decrease the current consumption of active microphones, since the MICGND pin is made Hi-Z when the microphone input is not selected (SL = LINE_IN_L in Record Select register (0x1A)). The LNA gain can be set to 0 or 20 dB via the 20 dB bit in the MIC Volume register (0x0E). Additional gain in 1.5 dB steps is possible via the GL[3:0] in the Record Gain register (0x1C).
UCB1400
AVDD AVDD
UCB1400
MICP
MICP
MICGND
MICGND
AVSS
AVSS
SN00226
SN00227
a.
`Passive' microphone.
b.
`Active' microphone.
Fig 15. Possible microphone connections.
9.1.3
Decimation filter The decimation from 128 fs is performed in two stages. The first stage realizes sin(x)/x characteristics with decimation factor of 16. The second stage consists of 3 half-band filters, each decimating by a factor of 2. The filter characteristics are shown in Table 6.
Table 6: Item Pass-band ripple Stop band Dynamic range Decimation filter characteristics Condition 0 to 0.45 fs > 0.55 fs 0 to 0.45 fs Value (dB) 0.015 -60 > 135
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Two bits in the Feature Control/Status Register 1 (0x6A) provide control over DC filtering:
* DC bit: controls the DC filter before the decimator used to compensate the DC
offset is added in the ADC to remove idle tones from the audio band.
* HIPS bit: controls the DC filter at the output of the decimation filter.
9.1.4 Overload detection An overload detection circuit will inform the user whenever the input voltage exceeds the maximum input voltage, which will lead to a high distortion. In that case, the OVFL bit in the Feature Control/Status Register 1 (0x6A) is set. In addition, an interrupt is generated on the IRQOUT pin of the UCB1400 whenever the OVLP bit or the OVLN bit is set in the Positive and/or Negative INT Enable Registers.
9.2 Interpolation filter (DAC)
The digital interpolation filter interpolates from 1 fs to 128 fs by means of a cascade of FIR filters. The filter characteristics are shown in Table 7.
Table 7: Item Pass-band ripple Stop band Dynamic range Interpolation filter characteristics Condition 0 to 0.45 fs > 0.55 fs 0 to 0.45 fs Value (dB) 0.025 -65 > 135
9.2.1
DSP features The UCB1400 supports the following DSP (Digital Sound Processing) features through the Feature Control/Status register 1 (0x6A):
* Tone control: Bass Boost (BB[3:0]) and Treble Boost (TR[1:0]) * Flat/Minimum/Maximum setting for bass and treble boost (M[1:0]) * De-emphasis control (DE bit)
In addition, the UCB1400 supports volume control and soft muting via the Master Volume register (0x02):
* Master volume control: The output level can be attenuated in 1.5 dB steps down to
-94.5 dB independently for the left and right channels via the Master Volume Register (0x02).
* Mute: The output is muted when the MM bit in the Master Volume Register is set.
Muting the DAC will result in a cosine roll-off soft mute, using 128 samples in the normal mode: this results in 3 ms at fs = 44.1 kHz. 9.2.2 Noise shaper The 3rd-order noise shaper operates at 128 fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream Digital-to-Analog Converter (FSDAC).
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9.2.3
Filter stream DAC The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way, very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage.
9.2.4
Headphone driver The headphone driver a reference output that acts as the virtual ground. This allows direct connection to a stereo headphone without the use of external DC blocking capacitors. The headphone driver is enabled when HPEN is set to `1' in the Feature Control/Status Register 1 (0x6A). The headphone driver is equipped with a short circuit protection on each of the LINE_OUT_L, LINE_OUT_R and VREFDRV output. When HPEN = 1, the short circuit protection circuit will inform the user in case the limiter is activated, e.g., in case of short circuit, by setting the corresponding bit (CLPL, CLPR or CLPG) in the Extra Interrupt register (0x70). In addition, an interrupt is generated on the IRQOUT pin of UCB1400 whenever the CLPP or CLPN bit is set in the Positive and/or Negative INT Enable Registers. In that case, the CPLS bit will be set in the INT Clear/Status register (index 0x62). The user can subsequently examine the Extra Interrupt register (0x70) to determine the source of the short circuit.
UCB1400
LINE_OUT_L
VREFDRV
LINE_OUT_R
SN00228
Fig 16. Headphone connections.
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9.3 Loopback mode
The audio codec incorporates a loopback mode, in which codec input path and output path are connected in series. It is activated when the LPBK bit in the General Purpose register (0x20) set. The loopback internally connects the digital output from the decimator of the ADC to the digital input of the Interpolator of the DAC, allowing for codec testing without the use of the AC Link.
9.4 PLL and sample rates
The audio sample rate is derived from the 24.576 MHz crystal clock for 8, 12, 16, 24, 32, and 48 kHz sample rates, and from the built-in PLL for 11.025, 22.05 and 44.1 kHz sample rates. The ADC and DAC can run at independent sample rates and are controlled by the ADC and DAC Sample Rate registers (0x32 and 0x2C).
9.5 Power-down modes
The audio input and output paths can be powered down independently; the input path is powered down when the PR0 bit in the Power-down Control/Status register (0x26) is set. The output path is disabled when the PR1 bit of the same register is set. This provides the user the means to reduce the current consumption of UCB1400 if one part of the audio codec is not used in the application. When both the input and output paths are disabled, the PR3 bit of the same register can also be set to turn off the audio reference to further reduce power consumption. If the Smart Low Power bits (SLP0 and SLP1) are set in the Feature Control/Status Register 2 (0x6C), the UCB1400 will power down unused blocks in the audio ADC analog front end and the PLL in a smart way, ensuring the lowest power consumption in each audio operating mode.
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10. Touch screen interface
10.1 Universal touch screen matrix
The UCB1400 contains a universal touch screen interface for 4-wire resistive touch screen, capable of performing position, pressure and plate resistance measurements. In addition, the touch screen can be programmed to generate interrupts when the touch screen is pressed. The last mode is also active when the UCB1400 is set in the stand-by mode.
TSPX
TSMX
TSPY
TSMY
TM[1:0]=00 AVDD
PXP, MXP, PYP, MYP
TOUCH SCREEN BIAS VOLTAGE
PXG, MXG, PYG, MYG
1 k TM[1:0] = 00 OR 1X AVSS AD[3:0] 7:4 AI[2:0] 0 1 2 ANALOG MUX 3 TOUCH SCREEN CURRENT MONITOR AVSS BIAS
0 ANALOG MUX
1 TM[1:0] = 01
TO ADC INPUT
SN00246
Fig 17. Block diagram of the touch screen interface.
The touch screen interface connects to the touch screen by four wires: TSPX, TSMX, TSPY and TSMY. Each of these pins can be programmed to be floating, powered or grounded in the touch screen switch matrix. The setting of each touch screen pin is programmable by the PXP, MXP, PYP, MYP and PXG, MYG, PYG, MYG bits in the touch screen control register. Possible conflicting settings (grounding and powering of a touch screen pin at the same time) are detected by the UCB1400. In that case, the UCB1400 will ground the touch screen pin. Each of the four touch screen signals can be selected as input for the built-in 10-bit ADC, which is used to determine the voltage on the selected touch screen pin in position measurement mode. In addition, the UCB1400 can monitor touch screen current via an internal 1 k resistor that can act as the input to the 10-bit ADC in pressure or plate resistance measurement mode. The flexible switch matrix and the multi-functional touch screen bias circuit enable the user of the UCB1400 to set each desired touch screen configuration.
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The UCB1400's internal voltage reference (Vref) acts as the reference voltage for the touch screen bias circuitry. This makes the touch screen biasing independent of supply voltage and temperature variations. Four low pass filters, one on each touch screen terminal, are built in to minimize the noise coupled from the LCD into the touch screen signals. An LCD typically generates large noise glitches on the touch screen, since they are closely coupled. The setting of the touch screen bias circuitry and the ADC multiplexer is determined by the setting of TM[1:0] in the touch screen control register according to Table 8.
Table 8: TM[1:0] 00 01 10 11 Touch screen mode selection Selected mode Interrupt Pressure Position Position Touch screen bias source Resistor to AVDD Touch screen bias circuit Touch screen bias circuit Touch screen bias circuit ADC multiplexer setting Defined by AI[2:0] Touch screen current monitor Defined by AI[2:0] Defined by AI[2:0]
10.2 Operational modes
The UCB1400 supports three modes of touch screen measurements: position, pressure, and plate resistances. Additionally, an interrupt mode is provided for detection of touch events. 10.2.1 Position measurement
VBIAS TOUCH RX2 RX1 TSMY TSMX Rt TSMX TSPY TSPY RY1 RY2 TO ADC VBIAS TSPX TSPX TO ADC
TSMY
SN00247
Fig 18. Touch screen setup for X position measurement.
Two position (X, Y) measurements are needed to determine the location of the pressed spot. The X plate is biased during the X position measurement and the voltage on one or both Y terminals (TSPY, TSMY) is measured. The circuit can be represented by a potentiometer, with the TSPY and/or TSMY electrode being the `wiper'. The measured voltage on the TSPY/TSMY terminal is proportional to the X position of the pressed spot of the touch screen. In the Y position mode, the X plate and Y plate terminals are interchanged, thus the Y plate is biased and the voltage on the TSPX and/or TSMX terminal is measured.
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10.2.2
Pressure measurement
VBIAS TOUCH RX2 VBIAS TSMX RX1 TSMY Rt TSMX TSPX VBIAS TSPX
VBIAS
TSPY TSPY
TSMY RY1 RY2
TO ADC TO ADC 1 k 1 k
SN00248
Fig 19. Touch screen setup for pressure-1 measurement (see Table 9).
The pressure applied to the touch screen can be determined. In fact, the contact resistance between the X and Y plates is measured, which is a good indication of the size of the pressed spot and the applied pressure. A soft stylus, e.g., a finger, leads to a rather large contact area between the two plates when a large pressure is applied. A hard stylus, e.g., a pen, leads to less variation in measured contact resistance since the contact area is rather small. One plate is biased at one or both terminals during this pressure measurement, whereas the other plate is grounded, again on one or both terminals. The current flowing through the touch screen is a direct indication for the resistance between both plates. A compensation for the series resistance, formed by the touch screen plates and the internal 1 k resistance of the UCB1400 will improve the accuracy of this measurement.
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10.2.3
Plate resistance measurement
VBIAS TSPX RX2 RX1 TO ADC 1 k TSMY RY1 RY2 TSPY TSMX TSMY Rt TSMX TO ADC TSPX
VBIAS
TSPY
1 k
SN00249
Fig 20. Touch screen setup for X plate resistance measurement.
The plate resistance of a touch screen varies a lot due to processing spreads. Knowing the actual plate resistance makes it possible to compensate for the plate resistance effects in the pressure resistance measurements. Secondly, the plate resistance decreases when two or more spots on the touch screen are pressed. In that case, a part of one plate, e.g., the X plate, is shorted by the other plate, which decreases the actual plate resistance. The plate resistance measurement is executed in the same way as the pressure resistance measurement. In this case, only one of the two plates is biased, and the other plate is kept floating. The current through the connected plate is again a direct indication of the connected resistance. 10.2.4 Interrupt mode
AVDD AVDD SCHMITT TRIGGER Rint
Rint
TOUCH RX2 RX1 Rt TSMX TSPY RY1 RY2 SCHMITT TRIGGER TSPX TSMY
TSPX
TSPY
TSMX TSMY
SN00250
Fig 21. Touch screen setup for interrupt detection.
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In addition to the measurements made above, the touch screen can also act as an interrupt source. In this mode, the X plate of the touch screen has to be powered, and the Y plate has to be grounded. In this case, the touch screen is not biased by the active touch screen bias circuit, but by a resistor to AVDD. This configuration simply biases the touch screen and the UCB1400 does not consume power unless the touch screen is touched. The voltage on the X plate terminals drops if the screen is pressed. This voltage drop is detected by Schmitt trigger circuits, of which the outputs are connected to the interrupt control block. A touch screen interrupt is generated either when the touch screen is pressed (falling edge enabled) or when the touch screen is released (rising edge enabled), which can be used to activate the system around the UCB1400 to start a touch screen readout sequence. The internal Schmitt trigger circuits are connected to the TSPX and TSMX signals after the built-in low-pass filters. This reduces the number of spurious interrupts, due to the coupling between the LCD screen and the touch screen sensors. 10.2.5
Table 9:
Mode summary
Measurement mode summary PXP 1 0 1 1 0 0 0 1 0 1 PXG 0 0 0 0 0 0 1 0 0 0 MXP 0 0 1 0 0 1 0 0 0 1 MXG 1 0 0 0 1 0 0 1 0 0 PYP 0 1 0 0 1 0 0 0 1 0 PYG 0 0 1 1 0 0 0 0 0 1 MYP 0 0 0 0 0 0 1 0 0 0 MYG 0 1 1 0 0 1 0 0 1 1 BIAS 1 1 1 1 1 1 1 1 1 0 TM 2 2 1 1 1 1 1 1 1 0 AI 2 or 3 0 or 1 Any Any Any Any Any Any Any Any
Touch screen measurement X position[1] Y position[1] Pressure Pressure Pressure Pressure 1[2] 2[2] 3[2] 5[2]
Pressure - 4[2] X plate resistance Y plate resistance Interrupt
[1] [2]
For X and Y position measurements, (PXP, PXG, PYP, PYG) can be swapped with (MXP, MXG, MYP, MYG) to get readings reversed in direction. For pressure measurements, (PXP, PXG, PYP, PYG) can be swapped with (MXP, MXG, MYP, MYG) to get the same readings with current flowing in the opposite direction.
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11. 10-bit ADC
The UCB1400 includes a 10-bit successive approximation analog-to-digital converter (ADC) with built-in track-and-hold circuitry, and an analog multiplexer to select one of the four analog inputs (AD0-3), the four touch screen inputs (TSPX, TSMX, TSPY, TSMY) or the current of the touch screen bias circuit. The analog multiplexer contains four resistive dividers to attenuate the high voltages on the AD0-3 inputs to the ADC input range.
CLOCK INTERNAL REFERENCE ADCSYNC
AD0 AD1 AD2 AD3 TSPX TSMX TSPY TSMY BIAS CURRENT INPUT MUX 10-BIT ADC ADC START/STOP LOGIC AS
TRACK AND HOLD
AE AI[2:0] TM[1:0] AD[9:0]
SN00240
Fig 22. Block diagram of the 10-bit ADC circuit.
The ADC is controlled through the AC '97 interface, but the UCB1400 contains internal logic to ease the control of the ADC and to minimize the number of AC '97 frame read/write actions. The ADC is activated by the AE bit in the ADC Control register (0x66). The ADC circuitry, including the track and hold circuitry does not consume any power as long as this bit is reset. The analog input multiplexer is controlled by the AI[2:0] bits and the ADC is actually started with the AS bit in the ADC Control register (0x66). A complete ADC control sequence consists of several phases. First the ADC has to be enabled; secondly, the input selector must be set to the proper input; thirdly, the ADC conversion has to be started; and finally, the ADC result has to be read from the ADC Data register (0x68). The UCB1400 has two different modes to start the ADC conversion, which are selected by the ASE bit in the ADC Control register (0x66). When ASE is `0', the ADC conversion is started directly by writing a `1' in the AS bit. If the AVE bit in the Feature/Control Status Register 2 (0x6C) is set to `1', additional filtering is applied to the ADC data, making it more immune to high frequency fluctuations in a noisy environment.
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When ASE is `1', the ADC is started at a rising edge of the signal applied to the ADCSYNC pin. In this mode, writing `1' to the AS bit will arm the ADC, such that it will start in the first detected rising edge of the ADCSYNC signal. A rising edge of the signal connected to the ADCSYNC pin occurring during the tracking time is ignored; the ADC conversion is started on the first rising edge detected after this delay time. This mode is particularly useful when the internal ADC has to be synchronized to the external system. Note that the AVE bit should not be set to `1' when ASE is `1'. The result of the conversion is stored in the ADC Data register (0x68), after the completion of the conversion. An interrupt may be generated whenever a conversion is completed (ADCP and/or ADCN bits in the Positive and Negative INT Enable registers) to ease the synchronization between the UCB1400 and the system controller. The ADV bit in the ADC Data register 0x68 indicates the status of the ADC data; it equals `0' when an ADC sequence is started, which implies that the ADC result is not valid, and it equals `1' when the ADC conversion is completed and the result is stored in the ADC Data register (0x68).
AD[n]
ADC INPUT MUX
AI[2:0]
SN00241
Fig 23. AD0-AD3 resistive dividers block diagram.
The applied voltage on the four analog inputs of the UCB1400 (AD0-AD3) is attenuated before it is applied to the ADC input multiplexer using on-chip resistive dividers. These high voltage inputs are optimized to handle voltages larger than the used supply voltage. The built-in resistive voltage dividers are only activated if the corresponding analog input is selected. The resistive dividers are made floating when the input is not selected by the ADC input multiplexer, such that the input leakage of these high voltage analog pins is minimized. This makes these analog inputs very suitable to monitor battery voltages.
11.1 On-chip reference circuit
The UCB1400 contains an on-chip reference voltage source, which generates the reference voltage for the 10-bit ADC and touch screen bias. The internal bandgap circuit is activated if the 10-bit ADC or touch screen function is activated. This reduces the current consumption of the UCB1400 in standby mode. The internal reference voltage is connected to the VREFBYP pin, where an external capacitor can be connected to filter this reference voltage, if the VREFB bit (register 0x66) is set to `1'.
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12. Register definition
The following tables describe the register definition for the UCB1400. The UCB1400 shall follow the AC '97 2.1 Interoperability Requirements and Recommendations as follows:
* Non-implemented or reserved register bits: All reserved or non-implemented
register bits (marked `X' in the tables) are required to return `0' when read.
* Non-implemented Addresses: Read access to non-implemented registers are
required to echo a `valid' 7-bit register address in Input Slot 1 and return `valid' 0x0000 data in Input Slot 2 on the next AC-link frame.
* Odd Register Addresses: Read (and write) access to odd register addresses are
required to be treated the same as non-implemented addresses, instead of aliasing them to the next lower even-numbered register.
* Codec register read data need to be returned in the next AC-link frame following
the frame in which the read request occurs.
* Codec-Ready and audio DAC/ADC status bits shall only change from `ready' to
`not ready' in response to a PR state change issued by the Controller to the Power-down Control/Status registers 0x26. This guarantees that once data is actively flowing on a slot, the Controller does not have to continuously read the Power-down Control/Status register to detect any unexpected Codec PR status change.
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Table 10: Register definitions Shaded registers are read-only. Reg Name (HEX) 00 02 0E 10-18 1A 1C 1E 20 Reset Master Volume MIC Volume Reserved Record Select Record Gain Reserved General Purpose Power-down Control/Status Ext'd Audio ID Ext'd Audio Status/Control D15 X MM X X X X RM X X X X ID1 X D14 X X X X X X X X X X X ID0 X D13 X ML5 X X X X X X X X PR5 X X DR13 X AR13 X X X TMXP D12 X ML4 X X X X X X X X PR4 X X D11 X ML3 X X X X GL3 X X X PR3 X X D10 X ML2 X X X SL2 GL2 X X X X X X D9 ID9 ML1 X X X SL1 GL1 X X X PR1 X X D8 X ML0 X X X SL0 GL0 X X X PR0 X X DR8 X AR8 X IO8 D7 ID7 X X X X X X X D6 X X X 20dB X X X X D5 ID5 MR5 X X X X X X X X X X X DR5 X AR5 X IO5 IOD5 IOP5 D4 X MR4 X X X X X X X X X X X DR4 X AR4 X IO4 D3 X MR3 X X X X GR3 X X X REF X X DR3 X AR3 X IO3 D2 X MR2 X X X SR2 GR2 X X X X X X DR2 X AR2 X IO2 D1 X MR1 X X X SR1 GR1 X X X DAC X X DR1 X AR1 X IO1 IOD1 IOP1 D0 X MR0 X X X SR0 GR0 X X X ADC VRA VRA DR0 X AR0 X IO0 Default (HEX) 02A0 8000 X 0000 X 0000 8000 X 0000 X 000X 0001 0000 BB80
04-0C Reserved
LPBK X X X X X DR7 X AR7 X IO7 X X X X DR6 X AR6 X IO6 IOD6 IOP6
1E-24 Reserved 26 28 2A 2C 32 34-58 5A 5C 5E
Audio DAC rate DR15 DR14 X X X X X X X X Audio ADC rate AR15 AR14 Reserved IO data IO direction Positive INT enable
DR12 DR11 DR10 DR9 X X X X X X X X X X X X X X IO9 AR12 AR11 AR10 AR9
Audio codec with touch screen controller and power management monitor
2E-30 Reserved
X BB80 X 0000
IOD9 IOD8 IOD7 IOP9 IOP8 IOP7
IOD4 IOD3 IOD2 IOP4 IOP3 IOP2
IOD0 0000 IOP0 0000
OVLP CLPP
TPXP ADCP X
UCB1400
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Table 10: Register definitions...continued Shaded registers are read-only. Reg Name (HEX) 60 62 64 66 68 6A 6C 6E
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D15
D14
D13 TMXN TMXS MX X X BB2 SUEV 0 X CLPG X 0 0
D12
D11
D10
D9
D8
D7
D6 ION6 IOS6 MYG X AD6 X TM6 X X 1 0
D5 ION5 IOS5 PXG
D4
D3
D2
D1 ION1 IOS1 PXP
D0
Default (HEX)
Negative INT enable Touch Screen control ADC control ADC data Feature CSR1 Feature CSR2 Test Control Extra Interrupt Reserved Vendor ID1 Vendor ID2
OVLN CLPN
TPXN ADCN X TPXS ADCS X PX X X BB1 AVE X X X 1 0 BIAS X X BB0
ION9 ION8 ION7 IOS9 IOS8 IOS7 TM0 X AD8 M1 X X X X 0 1 PYG AS AD7 M0 X X X X 0 0
ION4 ION3 ION2 IOS4 IOS3 IOS2 MXG PYP AI1 AD3 MYP AI0 AD2 EV2 TM2 X X 0 1
ION0 0000 IOS0 0000 MXP 0000 0000 0000 0000 XXXX 0000 X 5053 4304
INT clear/status OVLS CLPS X AE ADV X SMT X X 0 0 X X X BB3 SUEV 1 X X 1 1
HYSD TM1 X X TR1 X AD9 TR0
EXVEN AI2 AD5 SLP1 TM5 X X 0 0 AD4 DC
VREFB ASE AD1 EV1 TM1 X X 1 0 AD0 EV0 TM0 X X 1 0
HPEN DE
HIPS GIEN X
OVFL 0000
AVEN AVEN X 1 0 X X X 0 0 X X X 0 0 X X X 0 1
SLP0 X TM4 X X 1 0 TM3 X X 0 0
70 7A 7C 7E
CLPL CLPR
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UCB1400
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12.1 Reset register (index 0x00)
Table 11: Reset register Register address: 0x00; default: 02A0 Bit Symbol Bit Symbol Table 12: Bit D15 - D10 D9 D8 D7 D6 D5 D4 - D0 D15 X D7 ID7 D14 X D6 X D13 X D5 ID5 D12 X D4 X D11 X D3 X D10 X D2 X D9 ID9 D1 X D8 X D0 X
Description of Reset register bits Symbol X ID9 X ID7 X ID5 X Type R R R R R R R Description Reserved. Always `1' (20-bit ADC resolution supported). Reserved. Always `1' (20-bit DAC resolution supported). Reserved. Always `1' (Loudness (bass boost) supported). Reserved.
Writing any value to this register performs a register reset, which causes all registers to revert to their default values.
12.2 Master Volume register (index 0x02)
Table 13: Master Volume register Register address: 0x02; default: 8000 Bit Symbol Bit Symbol Table 14: Bit D15 D14 D13 - D8 D7 - D6 D5 - D0 D15 MM D7 X D14 X D6 X D13 ML5 D5 MR5 D12 ML4 D4 MR4 D11 ML3 D3 MR3 D10 ML2 D2 MR2 D9 ML1 D1 MR1 D8 ML0 D0 MR0
Description of Master Volume register bits Symbol MM X ML5 - ML0 X MR5 - MR0 Type RW R RW R RW Description Master mute. Reserved. Left channel attenuation in 1.5 dB step (000000 = 0 dB; 111111 = -94.5 dB). Reserved. Right channel attenuation in 1.5 dB step (000000 = 0 dB; 111111 = -94.5 dB).
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12.3 MIC Volume register (index 0x0E)
Table 15: MIC Volume register Register address: 0x0E; default: 0000 Bit Symbol Bit Symbol Table 16: Bit D15 - D7 D6 D5 - D0 D15 X D7 X D14 X D6 20dB D13 X D5 X D12 X D4 X D11 X D3 X D10 X D2 X D9 X D1 X D8 X D0 X
Description of MIC Volume register bits Symbol X 20dB X Type R RW R Description Reserved. 20 dB boost. Reserved.
12.4 Record Select register (index 0x1A)
Table 17: Record Select register Register address: 0x1A; default: 0000 Bit Symbol Bit Symbol Table 18: Bit D15 - D11 D10 - D8 D7 - D3 D2 - D0 D15 X D7 X D14 X D6 X D13 X D5 X D12 X D4 X D11 X D3 X D10 SL2 D2 SR2 D9 SL1 D1 SR1 D8 SL0 D0 SR0
Description of Record Select register bits Symbol X SL2 - SL0 X SR2 - SR0 Type R RW R RW Description Reserved. Left record source (000 = MIC; 100 = Line In L; other values reserved). Reserved. Right record source (000 = Copy Left; 100 = Line In R; other values reserved). When SR = 000, the right record channel copies data from left record channel to create mono data and gain and sample rate control can only be made via the left channel. This mode is primarily intended when the mono MIC input is selected at the left channel (SL = 000).
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12.5 Record Gain register (index 0x1C)
Table 19: Record Gain register Register address: 0x1C; default: 8000 Bit Symbol Bit Symbol Table 20: Bit D15 D14 - D12 D11 - D8 D7 - D4 D3 - D0 D15 RM D7 X D14 X D6 X D13 X D5 X D12 X D4 X D11 GL3 D3 GR3 D10 GL2 D2 GR2 D9 GL1 D1 GR1 D8 GL0 D0 GR0
Description of Master Volume register bits Symbol RM X GL3 - GL0 X GR3 - GR0 Type RW R RW R RW Description Master Record mute. Reserved. Left channel record gain in steps of 1.5 dB (0000 = 0 dB; 1111 = 22.5 dB). Reserved. Right channel record gain in steps of 1.5 dB (0000 = 0 dB; 1111 = 22.5 dB).
12.6 General Purpose register (index 0x20)
Table 21: General Purpose register Register address: 0x20; default: 0000 Bit Symbol Bit Symbol Table 22: Bit D15 - D8 D7 D6 - D0 D15 X D7 LPBK D14 X D6 X D13 X D5 X D12 X D4 X D11 X D3 X D10 X D2 X D9 X D1 X D8 X D0 X
Description of General Purpose register bits Symbol X LPBK X Type R RW R Description Reserved. ADC/DAC loopback mode (ADC output to DAC input). Reserved.
The LPBK bit enables loopback of the ADC output to the DAC input without involving the AC-link, allowing for full system performance measurements.
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12.7 Power-down Control/Status register (index 0x26)
Table 23: Power-down Control/Status register Register address: 0x26; default: 000X Bit Symbol Bit Symbol Table 24: Bit D15 - D14 D13 D12 D11 D10 D9 D8 D7 - D4 D3 D2 D1 D0 D15 X D7 X D14 X D6 X D13 PR5 D5 X D12 PR4 D4 X D11 PR3 D3 REF D10 X D2 X D9 PR1 D1 DAC D8 PR0 D0 ADC
Description of Power-down Control/Status register bits Symbol X PR5 PR4 PR3 X PR1 PR0 X REF X DAC ADC Type R RW RW RW R RW RW R R R R R Description Reserved. Internal clock disable. Digital interface (AC-link) power-down (external clock off). Audio VREF power-down. Reserved. Audio DAC and output path power-down. Audio ADC and input path power-down. Reserved. Audio VREF up to nominal level. Reserved. Audio DAC section ready to accept data. Audio ADC section ready to transmit data.
This read/write register is used to program power-down states and monitor subsystem readiness. The lower half of this register is read only status, a `1' indicating that the subsection is `ready'. `Ready' is defined as the subsection able to perform in its nominal state. When this register is written, the bit values that come in on AC-link will have no effect on read-only bits 0 - 7. When the `Codec Ready' indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the UCB1400 control and status registers are in a fully operational state. The AC '97 Controller must further probe this Power-down Control/Status register to determine exactly which subsections, if any, are ready.
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12.8 Extended Audio ID register (index 0x28)
Table 25: Extended Audio ID register Register address: 0x28; default: 0001 Bit Symbol Bit Symbol Table 26: Bit D15 - D14 D13 - D1 D0 D15 ID1 D7 X D14 ID0 D6 X D13 X D5 X D12 X D4 X D11 X D3 X D10 X D2 X D9 X D1 X D8 X D0 VRA
Description of Extended Audio ID register bits Symbol ID1 - ID0 X VRA Type R R R Description Always `0' (UCB1400 is a primary codec). Reserved. Always `1' (Variable Rate PCM Audio supported).
The Extended Audio ID is a read-only register that identifies which extended audio features are supported (in addition to the original AC '97 features identified by reading the Reset register at Index 0x00).
12.9 Extended Audio Status and Control register (index 0x2A)
Table 27: Extended Audio Status and Control register Register address: 0x2A; default: 0000 Bit Symbol Bit Symbol Table 28: Bit D15 - D1 D0 D15 X D7 X D14 X D6 X D13 X D5 X D12 X D4 X D11 X D3 X D10 X D2 X D9 X D1 X D8 X D0 VRA
Description of Extended Audio Status and Control register bits Symbol X VRA Type R RW Description Reserved. 1 enables Variable Rate Audio mode (sample rate control registers and SLOTREQ signalling).
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12.10 Audio Sample Rate Control register (index 0x2C and 0x32)
Table 29: Audio DAC Sample Rate Control register Register address: 0x2C; default: BB80 Bit Symbol Bit Symbol D15 DR15 D7 DR7 D14 DR14 D6 DR6 D13 DR13 D5 DR5 D12 DR12 D4 DR4 D11 DR11 D3 DR3 D10 DR10 D2 DR2 D9 DR9 D1 DR1 D8 DR8 D0 DR0
Table 30: Audio ADC Sample Rate Control register Register address: 0x32; default: BB80 Bit Symbol Bit Symbol D15 AR15 D7 AR7 D14 AR14 D6 AR6 D13 AR13 D5 AR5 D12 AR12 D4 AR4 D11 AR11 D3 AR3 D10 AR10 D2 AR2 D9 AR9 D1 AR1 D8 AR8 D0 AR0
The sample rate control registers contain 16-bit unsigned values between 0 and 65535, representing the rate of operation in Hz. Table 31 shows the sample rates supported by UCB1400. In VRA mode (VRA = 1 in register 0x2A), if the value written to the register is supported, that value will be echoed back when read, otherwise the closest (higher in case of a tie) sample rate supported is returned. The UCB1400's DAC and ADC are capable of operating at independent rates. In non-VRA mode (VRA = 0 in register 0x2A), the only supported sample rate is 48 kHz.
Table 31: 8000 11025 12000 16000 22050 24000 32000 44100 48000 Supported sample rates D15 - D0 1F40 2B11 2EE0 3E80 5622 5DC0 7D00 AC44 BB80
Sample rate (MHz)
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12.11 IO Data register (index 0x5A)
Table 32: IO Data register Register address: 0x5A; default: 0000 Bit Symbol Bit Symbol Table 33: Bit D15 - D10 D9 - D0 D15 X D7 IO7 D14 X D6 IO6 D13 X D5 IO5 D12 X D4 IO4 D11 X D3 IO3 D10 X D2 IO2 D9 IO9 D1 IO1 D8 IO8 D0 IO0
Description of IO Data register bits Symbol X IO9 - IO0 Type R RW Description Reserved. When read, this register returns the actual state of all IO pins. When written, each register bit will be transferred to the corresponding IO pin programmed as output.
12.12 IO Direction register (index 0x5C)
Table 34: IO Direction register Register address: 0x5C; default: 0000 Bit Symbol Bit Symbol Table 35: Bit D15 - D10 D9 - D0 D15 X D7 IOD7 D14 X D6 IOD6 D13 X D5 IOD5 D12 X D4 IOD4 D11 X D3 IOD3 D10 X D2 IOD2 D9 IOD9 D1 IOD1 D8 IOD8 D0 IOD0
Description of IO Direction register bits Symbol X IOD9 - IOD0 Type R RW Description Reserved. If a bit is `1', the associated IO pin is defined as output. If a bit is `0', the associated IO pin is defined as input.
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12.13 Positive INT Enable register (index 0x5E)
Table 36: Positive INT Enable register Register address: 0x5E; default: 0000 Bit Symbol Bit Symbol Table 37: Bit D15 D14 D13 D12 D11 D10 D9 - D0 D15 OVLP D7 IOP7 D14 CLPP D6 IOP6 D13 TMXP D5 IOP5 D12 TPXP D4 IOP4 D11 ADCP D3 IOP3 D10 X D2 IOP2 D9 IOP9 D1 IOP1 D8 IOP8 D0 IOP0
Description of Positive INT Enable register bits Symbol OVLP CLPP TMXP TPXP ADCP X IOP9 - IOP0 Type RW RW RW RW RW R RW Description If `1', the rising edge interrupt of the OVFL signal is enabled. If `1', the rising edge interrupt of the CLIP signal is enabled. If `1', the rising edge interrupt of the TSMX signal is enabled. If `1', the rising edge interrupt of the TSPX signal is enabled. If `1', the rising edge interrupt of ADC Ready is enabled. Reserved. If a bit is `1', the rising edge interrupt of the associated IO pin is enabled.
12.14 Negative INT Enable register (index 0x60)
Table 38: Negative INT Enable register Register address: 0x60; default: 0000 Bit Symbol Bit Symbol Table 39: Bit D15 D14 D13 D12 D11 D10 D9 - D0 D15 OVLN D7 ION7 D14 CLPN D6 ION6 D13 TMXN D5 ION5 D12 TPXN D4 ION4 D11 ADCN D3 ION3 D10 X D2 ION2 D9 ION9 D1 ION1 D8 ION8 D0 ION0
Description of Negative INT Enable register bits Symbol OVLN CLPN TMXN TPXN ADCN X ION9 - ION0 Type RW RW RW RW RW R RW Description If `1', the falling edge interrupt of the OVFL signal is enabled. If `1', the falling edge interrupt of the CLIP signal is enabled. If `1', the falling edge interrupt of the TSMX signal is enabled. If `1', the falling edge interrupt of the TSPX signal is enabled. If `1', the falling edge interrupt of ADC Ready is enabled. Reserved. If a bit is `1', the falling edge interrupt of the associated IO pin is enabled.
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12.15 INT Clear/Status register (index 0x62)
Table 40: INT Clear/Status register Register address: 0x62; default: 0000 Bit Symbol Bit Symbol Table 41: Bit D15 D14 D13 D12 D11 D10 D9 - D0 D15 OVLS D7 IOS7 D14 CLPS D6 IOS6 D13 TMXS D5 IOS5 D12 TPXS D4 IOS4 D11 ADCS D3 IOS3 D10 X D2 IOS2 D9 IOS9 D1 IOS1 D8 IOS8 D0 IOS0
Description of INT Clear/Status register bits Symbol OVLS CLPS TMXS TPXS ADCS X IOS9 - IOS0 Type RW RW RW RW RW R RW Description When read, returns the OVFL interrupt status. Cleared by writing `1' to this bit. When read, returns the CLIP interrupt status. Cleared by writing `1' to this bit. When read, returns the TSMX interrupt status. Cleared by writing `1' to this bit. When read, returns the TSPX interrupt status. Cleared by writing `1' to this bit. When read, returns the ADC Ready interrupt status. Cleared by writing `1' to this bit. Reserved. When read, returns all IO pin interrupt status. The interrupt status of a pin is cleared by writing `1' to the corresponding bit.
12.16 Touch Screen Control register (index 0x64)
Table 42: Touch Screen Control register Register address: 0x64; default: 0000 Bit Symbol Bit Symbol Table 43: Bit D15 - D14 D13 D15 X D7 PYG D14 X D6 MYG D13 MX D5 PXG D12 PX D4 MXG D11 BIAS D3 PYP D10 HYSD D2 MYP D9 TM1 D1 PXP D8 TM0 D0 MXP
Description of Touch Screen Control register bits Symbol X MX Type R R Description Reserved. State of the TSMX pin. 0 = low voltage (pen down) 1 = high voltage (pen up)
D12
PX
R
State of the TSPX pin. 0 = low voltage (pen down) 1 = high voltage (pen up)
D11
BIAS
RW
If `1', the touch screen bias circuitry is activated. If `0', the touch screen bias is disabled to minimize power consumption.
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Description of Touch Screen Control register bits...continued Symbol HYSD TM1 - TM0 Type RW RW Description If `1', hysteresis is deactivated on the Schmitt triggers. Touch screen operation mode 00 = interrupt mode 01 = pressure measurement mode 1x = position measurement mode
Table 43: Bit D10 D9 - D8
D7 D6 D5 D4 D3 D2 D1 D0
PYG MYG PXG MXG PYP MYP PXP MXP
RW RW RW RW RW RW RW RW
If `1', the TSPY pin is grounded. If `1', the TSMY pin is grounded. If `1', the TSPX pin is grounded. If `1', the TSMX pin is grounded. If `1', the TSPY pin is powered. If `1', the TSMY pin is powered. If `1', the TSPX pin is powered. If `1', the TSMX pin is powered.
12.17 ADC Control register (index 0x66)
Table 44: ADC Control register Register address: 0x66; default: 0000 Bit Symbol Bit Symbol Table 45: Bit D15 D14 - D8 D7 D6 D5 D4 - D2 D15 AE D7 AS D14 X D6 X D13 X D5 EXVEN D12 X D4 AI2 D11 X D3 AI1 D10 X D2 AI0 D9 X D1 VREFB D8 X D0 ASE
Description of ADC Control register bits Symbol AE X AS X EXVEN AI2 - AI0 Type RW R RW R R/W RW Description If `1', ADC is activated. If `0', ADC is powered-down. Reserved. Writing `1' starts the ADC conversion sequence. This bit self-clears. Reserved. Must be set to `0' (other values reserved for testing purposes only). ADC input selection: 000 = TSPX 001 = TSMX 010 = TSPY 011 = TSMY 100 = AD0 101 = AD1 110 = AD2 111 = AD3
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Description of ADC Control register bits...continued Symbol VREFB ASE Type R/W RW Description VREF bypass. If `1', the internal reference voltage is connected to VREFBYP pin. If `1', ADC is armed by the AS bit and started by a rising edge on the ADCSYNC pin. If `0', ADC is started by the AS bit.
Table 45: Bit D1 D0
12.18 ADC Data register (index 0x68)
Table 46: ADC Data register Register address: 0x68; default: 0000 Bit Symbol Bit Symbol Table 47: Bit D15 D15 ADV D7 AD7 D14 X D6 AD6 D13 X D5 AD5 D12 X D4 AD4 D11 X D3 AD3 D10 X D2 AD2 D9 AD9 D1 AD1 D8 AD8 D0 AD0
Description of ADC Data register bits Symbol ADV Type R Description `0' if ADC conversion is in progress. `1' if the ADC conversion is completed and the ADC data is stored in AD9 - AD0.
D14 - D10 D9 - D0
X AD9 - AD0
R R
Reserved. ADC data.
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12.19 Feature Control/Status Register 1 (index 0x6A)
Table 48: Feature Control/Status Register 1 Register address: 0x6A; default: 0000 Bit Symbol Bit Symbol Table 49: Bit D15 D14 - D11 D15 X D7 M0 D14 BB3 D6 X D13 BB2 D5 DE D12 BB1 D4 DC D11 BB0 D3 HIPS D10 TR1 D2 GIEN D9 TR0 D1 X D8 M1 D0 OVFL
Description of Feature Control/Status Register 1 bits Symbol X BB3 - BB0 Type R RW Description Reserved. Bass boost BB 0-9 10-12 13-15 M = Flat (dB) M = Min. (dB) M = Max. (dB) 0 0 0 2*BB 18 18 2*BB 2*BB 24
D10 - D9
TR1 - TR0
RW
Treble boost TR 0-3 M = Flat (dB) M = Min. (dB) M = Max. (dB) 0 2*TR 2*TR
D8 - D7
M1 - M0
RW
Mode 00 = flat 01 = minimum 10 = minimum 11 = maximum
D6 D5 D4 D3 D2
HPEN DE DC HIPS GIEN
RW RW RW R RW
If `1', headphone driver is enabled. If `1', de-emphasis is enabled when the sample rate is 48, 44.1 or 32 kHz. If `1', DC filter is enabled. If `1', activate high-pass filter in the decimator. If `1', the following interrupt/wake-up signalling is enabled:
* *
D1 D0 X OVFL R RW
Interrupt signalling via GPIO_INT (input slot 12) when BIT_CLK is on. Wake-up signalling via SDATA_IN when BIT_CLK is off.
Reserved. When read, returns ADC overflow status (set status is sticky until cleared). When written, clears ADC overflow status.
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12.20 Feature Control/Status Register 2 (index 0x6C)
Table 50: Feature Control/Status Register 2 Register address: 0x6C; default: 0000 Bit Symbol Bit Symbol Table 51: Bit D15 D14 - D13 D12 D11 - D10 D5 - D4 D15 SMT D7 X D14 SUEV1 D6 X D13 SUEV0 D5 SLP1 D12 AVE D4 SLP0 D11 AVEN1 D3 X D10 AVEN0 D2 EV2 D9 X D1 EV1 D8 X D0 EV0
Description of Feature Control/Status Register 2 bits Symbol SMT SUEV1 SUEV0 AVE AVEN1 AVEN0 SLP1 SLP0 Type RW RW RW RW RW Description Must be set to `0' (other values reserved for testing purposes only). Must be set to `0' (other values reserved for testing purposes only). If `1', ADC Filter is enabled. Must be set to `0' (other values reserved for testing purposes only).
* * *
0: no Smart Low Power Mode. On normal mode operation, all Codec input blocks and PLL are ON. 1: Smart Low Power Mode on the Codec only. On normal mode operation, only used input stage(s) is/are ON. PLL remains ON all the time. 2: Smart Low Power Mode on the PLL only. On normal mode operation, PLL is ON only when a sample rate equal to 11.025, 22.05, or 44.1 kHz is selected and the corresponding audio ADC or DAC is not in power-down mode. Codec input blocks are always ON.
*
D2 - D0 EV2 - EV0 RW
3: Smart Low Power Mode on both Codec and PLL.
Must be set to `0' (other values reserved for testing purposes only).
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12.21 Test Control register (index 0x6E)
Table 52: Test Control register Register address: 0x6E; default: XXXX Bit Symbol Bit Symbol Table 53: Bit D15 - D7 D6 - D0 D15 X D7 X D14 X D6 TM6 D13 X D5 TM5 D12 X D4 TM4 D11 X D3 TM3 D10 X D2 TM2 D9 X D1 TM1 D8 X D0 TM0
Description of Test Control register bits Symbol X TM6 - TM0 Type R RW Description Reserved. Test mode. Reserved for testing purposes only.
This register cannot be reset and is not scan testable. It has no effect until the UCB1400 is put in Vendor-Specific Test Mode (refer to Section 8.7.2).
12.22 Extra Interrupt register (index 0x70)
Table 54: Extra Interrupt register Register address: 0x70; default: 0000 Bit Symbol Bit Symbol Table 55: Bit D15 D14 D13 D12 - D0 D15 CLPL D7 X D14 CLPR D6 X D13 CLPG D5 X D12 X D4 X D11 X D3 X D10 X D2 X D9 X D1 X D8 X D0 X
Description of ADC Data register bits Symbol CLPL CLPR CLPG X Type RW RW RW R Description Status of the CLIPL (LINE_OUT_L short circuit) signal; write `1' to clear. Status of the CLIPR (LINE_OUT_R short circuit) signal; write `1' to clear. Status of the CLIPGND (VREFDRV short circuit) signal; write `1' to clear. Reserved.
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12.23 Vendor ID1 and ID2 registers (index 0x7C and 0x7E)
Table 56: Vendor ID1 register Register address: 0x7C; default: 5053 Bit Symbol Bit Symbol D15 0 D7 0 D14 1 D6 1 D13 0 D5 0 D12 1 D4 1 D11 0 D3 0 D10 0 D2 0 D9 0 D1 1 D8 0 D0 1
Table 57: Vendor ID2 register Register address: 0x7E; default: 4304 Bit Symbol Bit Symbol D15 0 D7 0 D14 1 D6 0 D13 0 D5 0 D12 0 D4 0 D11 0 D3 0 D10 0 D2 1 D9 1 D1 0 D8 1 D0 0
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13. Limiting values
Table 58: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tstg Tamb Ves Parameter Supply voltage Storage temperature Operating ambient temperature Electrostatic handling voltage Equivalent to discharging a 100 pF capacitor via 1.5 k series resistor Conditions Min -0.5 -65 -40 -1500 Max 4 +125 +85 +1500 Unit V C C V
14. Static characteristics
Table 59: Static characteristics DVDD = AVDD = VADCP = 3.3 V; Tamb = 25 C; all voltage measured with respect to ground; unless otherwise specified. Symbol Supply AVDD DVDD IDDD Analog supply voltage Digital supply voltage Digital supply current Full audio, Line-in selected Audio ADC only, Line-in selected Audio DAC and headphone driver only AC-link only Standby IDDA Analog supply current Full audio, Line-in selected Audio ADC only, Line-in selected Audio DAC and headphone driver only Touch screen bias only 10-bit ADC only Standby Digital input pins (5 V tolerant, TTL compatible) VIH VIL |IIL| Ci VOH VOL
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Parameter
Conditions
Min 3.0 3.0 - - - - - - - - - - - 2.0 -0.5 - -
Typ 3.3 3.3 18 12 13 7 1 12 8 4.5 0.9 1.8 3 - - - -
Max 3.6 3.6 - - - - - - - - - - - 5.5 0.8 1 10 - 0.4
Unit V V mA mA mA mA A mA mA mA mA mA A V V A pF V V
HIGH-level input voltage LOW-level input voltage Input leakage current Input capacitance HIGH-level output voltage LOW-level output voltage IOH = -2 mA IOL = 2 mA
Digital output pins 0.85 DVDD - - -
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15. Dynamic characteristics
Table 60: Dynamic characteristics DVDD = AVDD = VADCP = 3.3 V; Tamb = 25 C; all voltage measured with respect to ground; unless otherwise specified. Symbol Audio ADC VADCP VADCN RIL CIL RIM CIM ZMICGND Vi(rms) Positive reference voltage Negative reference voltage Line input resistance Line input capacitance MIC input resistance MIC input capacitance Impedance MICGND - VSSA FS input voltage (rms value) Line inputs MIC input Vi Unbalance between channels At -3 dB input At -60 dB input; A-weighted 20 dB = 0 20 dB = 1 ( THD + N ) Total harmonic distortion plus ---------------------------- noise-to-signal ratio; f = 48 kHz, S s Line-in selected S/N CS PSRR Record Gain = 0 dB - - - - - - - - - 1.0 1.0 0.1 0.1 -87 -37 97 95 30 - - - - - - - - - V V V dB dB dB dB dB dB - - - - - - - AVDD 0.0 10 24 10 24 - - - - - - - 200 V V k pF k pF Parameter Conditions Min Typ Max Unit
Signal-to-noise ratio; fs = 48 kHz, At zero input; A-weighted Line-in selected Channel separation; fs = 48 kHz, Line-in selected Power supply rejection ratio At 0 dB input fripple = 1 kHz; Vripple = 30 mV(p-p)
Audio DAC + headphone driver RL CL VVREFDRV Vo(rms) Po Vo Load resistance Load capacitance VREFDRV voltage Output voltage (rms value) Output power Unbalance between channels At 0 dB (FS) digital input RL = 10 k At 0 dB (FS) digital input RL = 32 At 0 dB (FS) digital input RL = 10 k At 0 dB digital input, RL = 32 At 0 dB digital input, RL = 10 k At -60 dB digital input; A-weighted S/N CS PSRR
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16 - - - - - - - - - - -
32 - AVDD/2 1.0 25 <0.1 -40 -80 -32 91 54 58
- 30 - - - - - - - - - -
pF V V mW dB dB dB dB dB dB dB
( THD + N ) Total harmonic distortion plus ---------------------------noise-to-signal ratio; fs = 48 kHz S
Signal-to-noise ratio Channel separation Power supply rejection ratio
Code = 0; A-weighted RL = 32 RL = 10 k; fripple = 1 kHz; Vripple = 30 mV(p-p)
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Table 60: Dynamic characteristics...continued DVDD = AVDD = VADCP = 3.3 V; Tamb = 25 C; all voltage measured with respect to ground; unless otherwise specified. Symbol Vi(bias) I Ri Rgs Rps RES Vi(AD0-AD3) Zi ILI LEd LEi ten td(s) Parameter Bias voltage Max. touch screen current Max. touch screen resistance to generate an interrupt Ground switch on resistance Power switch on resistance Resolution Full scale AD0-AD3 inputs Input impedance Input leakage current Differential linearity error Integral linearity error ADC enable time Sampling delay Non-synchronization mode (AS = 0, AVE = 0) Synchronization mode; rising edge ADCSYNC to sample moment (AS = 1, AVE = 0) tconv ttrack tadcsync Oscillator fosc Oscillator frequency - 24.576 - MHz Total conversion time Tracking time HIGH time ADSYNC signal AS = AVE = 0 21 - Tclk_period 1 - Tclk_period - - 81.4 10 2 - 3 Tclk_period - - s s ns VAD0 = VAD1 = VAD2 = VAD3 = 7.5 V Conditions Position mode selected; no loading Position mode selected Interrupt mode selected Min - 10 - - - - - - - Typ 1.89 - - - - 10 7.5 77 - 1 2 Max - - 2500 50 50 - 10 - - Unit V mA Bits V k A LSB LSB Touch screen
Voltage monitor ADC
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16. AC Link characteristics
Table 61: Characteristics DVDD = AVDD = VADCP = 3.3 V; Tamb = 25 C; all voltage measured with respect to ground; unless otherwise specified. Symbol Trst_low Trst2clk Tsync_high Tsync2clk Parameter RESET active-LOW pulse width (AC Link controller) RESET inactive to BIT_CLK start-up delay SYNC active-HIGH pulse width (AC Link controller) SYNC inactive to BIT_CLK start-up delay BIT_CLK frequency Tclk_period Tclk_high Tclk_low Tsync_period Tsync_high Tsync_low tco Tsetup Thold Triseclk Tfallclk Trisesync Tfallsync Trisedin Tfalldin Trisedout Tfalldout Ts2_pdown Tsetup2rst Toff BIT_CLK period BIT_CLK output jitter BIT_CLK HIGH pulse width BIT_CLK LOW pulse width SYNC frequency SYNC period SYNC HIGH pulse width SYNC LOW pulse width Output delay from rising edge of BIT_CLK Input setup to falling edge of BIT_CLK Input hold from falling edge of BIT_CLK BIT_CLK rise time BIT_CLK fall time SYNC rise time SYNC fall time SDATA_IN rise time SDATA_IN fall time SDATA_OUT rise time SDATA_OUT fall time End of Slot 2 to BIT_CLK, SDATA_IN LOW Setup to trailing edge of RESET (AC Link controller) Rising edge of RESET to Hi-Z delay Conditions Min 1.0 162.8 1.0 162.8 36 36 10 10 15 12.288 81.4 40.7 40.7 48.0 20.8 1.3 19.5 0.65 750 45 45 15 10 10 6 6 10 10 6 6 25 Typ Max Unit s ns s ns MHz ns ps ns ns kHz s s s ns ns ns ns ns ns ns ns ns ns ns s ns ns Cold/warm reset
AC-link clocks
Data setup and hold
AC-link low power mode ATE test mode
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17. Timing diagrams
Trst_low RESET
Trst2clk
BIT_CLK
SN00229
Fig 24. Cold reset timing.
Tsync_high SYNC
Tsync2clk
BIT_CLK
SN00230
Fig 25. Warm reset timing.
Tclk_high BIT_CLK Tclk_period
Tclk_low
Tsync_high SYNC Tsync_period
Tsync_low
SN00231
Fig 26. BIT_CLK and SYNC timing.
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tCO VIH
tsetup
BIT_CLK
VIL
SDATA_OUT SDATA_IN SYNC
VOH VOL thold
SN00232
Fig 27. Data output and input timing.
BIT_CLK Triseclk Tfall clk
SYNC Trisesync Tfall sync
SDATA_IN Trisedin Tfall din
SDATA_OUT Trisedout Tfall dout
SN00233
Fig 28. Data rise and fall timing.
SYNC
SLOT 1
SLOT 2
BIT_CLK
SDATA_OUT
WRITE TO 0x26
DATA PR4 Ts2_pdown
SDATA_IN
SN00234
BIT_CLK not to scale.
Fig 29. AC Link low power timing.
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RESET
SDATA_OUT Tsetup2rst SDATA_IN, BIT_CLK Toff Hi-Z
SN00235
Fig 30. ATE test mode timing.
18. Application information
AVdd +3.3 V
R1 10
DVdd +3.3 V
C1 22 uF
C3 22 uF
C4 0.1 uF
C2 22 uF C5 C6 0.1 uF C7 0.1 uF C8 0.1 uF C9 0.1 uF
BIT_CLK SYNC SDATA_IN SDATA_OUT RESET IRQOUT ADCSYNC MICP MICGND LINE_IN_L LINE_IN_R C14 47 uF AD0 AD1 AD2 AD3 TSMY TSPX TSPY TSMX C15 0.1 uF C10 4.7 uF C11 47 uF C12 47 uF
6 10 8 5 11 29 12 21 22 23 24
BIT_CLK SYNC SDATA_IN SDATA_OUT RESET IRQOUT ADCSYNC MICP MICGND LINE_IN_L LINE_IN_R
DVDD1 DVDD2 AVDD1 AVDD2 AVDD3
1 9 25 32 38
0.1 uF
LINE_OUT_L 35 LINE_OUT_R 36 VREFDRV 34 VREFBYP 30 C13 0.1 uF
LINE_OUT_L LINE_OUT_R VREFDRV
27 VREF 28 VADCP 31 VADCN 16 15 14 13 19 17 20 18 AD(0) AD(1) AD(2) AD(3) TSMY TSPX TSPY TSMX
UCB1400
GPIO(0) GPIO(1) GPIO(2) GPIO(3) GPIO(4) GPIO(5) GPIO(6) GPIO(7) GPIO(8) GPIO(9) DVSS1 DVSS2 AVSS1 AVSS2 AVSS3 37 39 40 41 43 44 45 46 47 48 4 7 26 33 42 R2 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9
2 XTL_IN Y1 3 XTL_OUT 24.576 MHz C16 33 pF C17 22 pF
SN00252
Fig 31. Typical application circuit.
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PROCESSOR POWER SUPPLY
MAIN BATTERY THERMISTOR
BACKUP (LITHIUM) SPARE SDATA_IN
SDATA_OUT
BIT_CLK
TOUCH SCREEN (RESISTIVE)
TOUCH I/F
MUX
VOLTAGE REFERENCE
10-BIT ADC
ADCSYNC
AC LINK I/O AND CONTROL
HEADPHONES 24.576 MHz OSC 2-CHANNEL 20-BIT AUDIO DAC POWERED SPEAKERS
GENERAL PURPOSE I/O PARTS
DIGITAL I/O
2-CHANNEL 20-BIT AUDIO ADC
CD PLAYER MIC
3.3V
Fig 32. Application block diagram.
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IRQOUT
RESET
SYNC
SN00238
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19. Package outline
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 EIAJ EUROPEAN PROJECTION
ISSUE DATE 99-12-27 00-01-19
Fig 33. LQFP48 (SOT313-2).
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20. Soldering
20.1 Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
20.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C small/thin packages.
20.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
* Use a double-wave soldering method comprising a turbulent wave with high
upward pressure followed by a smooth laminar wave.
* For packages with leads on two sides and a pitch (e):
- larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end.
* For packages with leads on four sides, the footprint must be placed at a 45 angle
to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
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During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
20.4 Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
20.5 Package related soldering information
Table 62: Package[1] BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[4], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO
[1] [2]
Suitability of surface mount IC packages for wave and reflow soldering methods Soldering method Wave not suitable not suitable[3] suitable not recommended[4][5] not recommended[6] Reflow[2] suitable suitable suitable suitable suitable
[3]
[4] [5] [6]
For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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21. Revision history
Table 63: Rev Date 02 20020621 Revision history CPCN Description Product data; second version; Engineering Change Notice 853-2358 28518; supersedes initial version UCB1400-01 of 03 Jan 2002 (9397 750 09242). Modifications:
* * * * * * *
01 20020103 -
Section 2 "Features" modified. Section 9.2.4 "Headphone driver" modified. Section 9.5 "Power-down modes" modified. Section 13 "Limiting values" modified: added Ves parameter. Section 14 "Static characteristics" modified. Section 15 "Dynamic characteristics" modified. Section 16 "AC Link characteristics" modified.
Objective data; initial version.
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22. Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] [2]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
23. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
24. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com.
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Audio codec with touch screen controller and power management monitor
Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 8.5 8.5.1 8.6 8.7 8.7.1 8.7.2 8.8 8.9 9 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.2 9.2.1 9.2.2 9.2.3 9.2.4 9.3 9.4 9.5 10 10.1 10.2 10.2.1 10.2.2 10.2.3 10.2.4 10.2.5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . 5 AC '97 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Resetting UCB1400 . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 AC-link digital serial interface protocol . . . . . . . . . . . . 7 AC-link audio output frame (SDATA_OUT). . . . . . . . . 8 AC-link audio input frame (SDATA_IN) . . . . . . . . . . . 10 AC-link low power mode. . . . . . . . . . . . . . . . . . . . . . 13 Accessing the UCB1400 . . . . . . . . . . . . . . . . . . . . . 14 Variable sample rate signaling protocol . . . . . . . . . . 16 SLOTREQ protocol . . . . . . . . . . . . . . . . . . . . . . . . . 16 Wake-up support . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ATE in-circuit test mode . . . . . . . . . . . . . . . . . . . . . . 17 Vendor-specific test mode . . . . . . . . . . . . . . . . . . . . 17 General purpose IOs . . . . . . . . . . . . . . . . . . . . . . . . 18 Interrupt generation . . . . . . . . . . . . . . . . . . . . . . . . . 18 Audio codec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ADC analog front-end . . . . . . . . . . . . . . . . . . . . . . . 20 Line inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Microphone input . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Decimation filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Overload detection . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Interpolation filter (DAC). . . . . . . . . . . . . . . . . . . . . . 22 DSP features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Noise shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Filter stream DAC. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Headphone driver. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PLL and sample rates . . . . . . . . . . . . . . . . . . . . . . . 24 Power-down modes . . . . . . . . . . . . . . . . . . . . . . . . . 24 Touch screen interface . . . . . . . . . . . . . . . . . . . . . . . 25 Universal touch screen matrix . . . . . . . . . . . . . . . . . 25 Operational modes. . . . . . . . . . . . . . . . . . . . . . . . . . 26 Position measurement . . . . . . . . . . . . . . . . . . . . . . . 26 Pressure measurement . . . . . . . . . . . . . . . . . . . . . . 27 Plate resistance measurement. . . . . . . . . . . . . . . . . 28 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Mode summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 11 11.1 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 12.10 12.11 12.12 12.13 12.14 12.15 12.16 12.17 12.18 12.19 12.20 12.21 12.22 12.23 13 14 15 16 17 18 19 20 20.1 20.2 20.3 20.4 20.5 21 22 23 24 10-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . On-chip reference circuit. . . . . . . . . . . . . . . . . . . . . . Register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset register (index 0x00). . . . . . . . . . . . . . . . . . . . Master Volume register (index 0x02) . . . . . . . . . . . . MIC Volume register (index 0x0E) . . . . . . . . . . . . . . Record Select register (index 0x1A) . . . . . . . . . . . . . Record Gain register (index 0x1C) . . . . . . . . . . . . . . General Purpose register (index 0x20) . . . . . . . . . . . Power-down Control/Status register (index 0x26). . . Extended Audio ID register (index 0x28) . . . . . . . . . Extended Audio Status and Control register (index 0x2A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Audio Sample Rate Control register (index 0x2C and 0x32). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IO Data register (index 0x5A) . . . . . . . . . . . . . . . . . . IO Direction register (index 0x5C). . . . . . . . . . . . . . . Positive INT Enable register (index 0x5E) . . . . . . . . Negative INT Enable register (index 0x60) . . . . . . . . INT Clear/Status register (index 0x62) . . . . . . . . . . . Touch Screen Control register (index 0x64) . . . . . . . ADC Control register (index 0x66) . . . . . . . . . . . . . . ADC Data register (index 0x68) . . . . . . . . . . . . . . . . Feature Control/Status Register 1 (index 0x6A) . . . . Feature Control/Status Register 2 (index 0x6C) . . . . Test Control register (index 0x6E). . . . . . . . . . . . . . . Extra Interrupt register (index 0x70) . . . . . . . . . . . . . Vendor ID1 and ID2 registers (index 0x7C and 0x7E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . AC Link characteristics . . . . . . . . . . . . . . . . . . . . . . . Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application information . . . . . . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction to soldering surface mount packages . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . Package related soldering information . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 31 32 35 35 36 36 37 37 38 39 39 40 41 41 42 42 43 43 44 45 46 47 48 48 49 50 50 51 53 54 56 58 59 59 59 59 60 60 61 62 62 62
(c) Koninklijke Philips Electronics N.V. 2002. Printed in the U.S.A
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 21 June 2002 Document order number: 9397 750 09611

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